Because PCIe has overshadowed PCI and PCI-X to a great extent, many are surprised to still see PCI slots on modern motherboards. And because they use parallel connections, many are also wondering how it could work with the serial PCIe. Let’s find out how that’s possible but before that, let’s first know the differences between the three PCI standards.
PCI, PCI-X, and PCIe
PCI was developed by Intel in the 1990s to replace the slower bus standards ISA, EISA, VLB, and MCA standards. The first version of PCI used a 32-bit bus operating at 33MHz and 5V signalling while the second version doubled the frequency to 66MHz with a 3.3V slot. A 64-bit variant was also developed later on. PCI provided a more satisfactory performance than the previous standards but it still wasn’t very suitable for servers.
An enhancement of PCI, PCI-X (PCI eXtended), operating at 133MHz on a 64-bit bus, was developed mainly to support servers. PCI-X 2.0 operated at an even higher frequency of 533 MHz. Both PCI and PCI-X implemented the parallel connection where the same bus connects several devices to the processor. A major downside of this architecture is that only one device can communicate with the host device at a time. The other devices have to wait for their turn before their requests can be processed. In turn, the performance degrades as more devices are added. New devices and applications also demand for faster speed and higher bandwidth and both the PCI and the PCI-X are just too slow to keep up with the demand. This called for a revamp of the bus interface giving birth to the latest PCI standard, the PCIe.
Instead of parallel connection, PCIe uses serial, point-to-point connection. Each device communicates to the processor through its own set of lanes so it can communicate directly with the processor without needing to wait for other devices. The serial communication of PCIe was the game changer and it significantly surpassed its predecessor’s performance. PCIe has reached five versions and each version doubles the bandwidth and transmission rate of the previous version. The latest version, PCIe 5.0, delivers an aggregate bandwidth of 128 GB/s on a x16 slot, leaping a hundredfold from the 1.06GB/s of PCI-X 2.0. PCIe has become the industry standard since the introduction of PCIe 1.0 and the older PCI and PCI-X became things of the past – or that’s what we thought.
Bridging Buses
PCIe is the underlying bus standard in modern motherboards, devices and expansion cards. However, some motherboards still have the legacy PCI/PCI-X slots on them which goes to show that PCI is still out there. PCI slots still exist for backward compatibility and they’re usually found in business-oriented computers. Most of the PCI cards used to be expensive and replacing a still working card just to keep up with the current technology seems to be impractical and costly for some businesses. Even some consumers still possess a traditional PCI card and a PCI slot on modern motherboards is a handy addition. Likewise, CPUs that use the PCI interface still exist and are still perfectly working. But how can these parallel components work with the serial interface? It is made possible with a PCIe Bridge.
A PCIe bridge is used to link devices that use the PCI or PCI-X interface to provide a PCIe connection to the processor, SoC, or root complex. PCIe bridges are typically installed in PCIe adapter cards, embedded computing, and motherboards so that PCI/PCI-X devices, PCI/PCI-X expansion slots, and even USB bus interfaces can still work with the serial architecture of PCIe. A PCIe bridge offers forward and reverse bridging capabilities for the PCIe device to work with a PCI/PCI-X device and vice versa.
Forward and Reverse Modes
PCIe bridges support Forward and Reverse bridging. Depending on which device takes on the primary and secondary side, the bridge can be configured in Forward and Reverse modes. In both modes, the PCIe bridge handles the interface conversion effectively with minimal impact to the PCI or PCIe hardware.
In Forward mode, the PCIe bridge connects a PCIe host device, which takes the primary side, to the PCI interface and ultimately to the PCI device. Some bridges also support fanout bridging where several PCI devices can be connected to the PCIe bridge to work with the PCIe host device. In this mode, the PCIe host device handles the PCIe bridge as the PCIe endpoint while the PCI device handles the PCIe bridge as the PCI host device.
On the other hand, in Reverse mode, the PCI host device takes on the primary side and connects to the PCIe bridge which is linked to the PCIe endpoint devices. The PCI host device handles the PCIe bridge as the PCI endpoint while the PCIe device handles the bridge as the PCIe host. This is mostly used to connect PCI CPUs to PCIe devices.
Conclusion
Contrary to what many think, the traditional parallel PCI is still around although it’s not as widely used as its most recent successor, the PCIe. Industries, and even the consumer market, continue to use the good old PCI and since the technology largely differs from PCIe, PCIe bridges were developed for modern systems to handle PCI devices. PCIe bridges fuse the two bus interfaces in a chip so both technologies can be interconnected despite the differences in architecture. We do not know for sure until when the PCI devices will be completely phased out, but while they are still here, the PCIe bridges are here to link them up.
